Credit Points: 3.5
Pipelined datapath and control, data hazards, forwarding, stalls, branch hazards, exceptions. Advanced pipelining, instruction level parallelism, issuing multiple instructions per cycle, hardware and compiler support for exploiting ILP, precise interrupts, example: the PowerPC 604. Memory hierarchy design, caches, reducing cache miss rate and miss penalty, reducing cache hit time, main memory, virtual memory, example: the Alpha 21064 memory hierarchy. Branch prediction, value prediction. Multiprocessors, cache coherence, synchronization. Embedded processors.