Course ID: 0512.4461

Credit Points: 3.5

Hours: 4

Prerequisites:  Computer Organization

History of computers. Technology Trends. Flynn’s Taxonomy. ISA Classes. Horizontal and Vertical Microcode. RISC vs CISC. Advanced Pipeline Datapath and Control. Hazards. Forwarding. Interlocks. Branch Hazards. Precise Interrupts and Exceptions. Multicycle and long pipelines.  The Memory Hierarchy. Direct Mapped Caches. Associative Caches. Basic Cache Optimizations. Virtual Memory. Advanced Cache Optimizations. Memory Technology. Software Techniques for Instruction Level Parallelism. Dependencies.  Loop Unrolling. Software Pipelining. Trace Scheduling. Predicated Instructions. VLIW. Hardware Techniques for Instruction Level Parallelism. Static Branch Prediction. Dynamic Branch Prediction. Dynamic Scheduling. Scoreboard. Tomsaulo. Speculation. Reorder Buffer. Explicit Renaming.   Limitations of ILP. Thread level Parallelism. Fine Grained TLP. Coarse Grained TLP. SMT. Shared Memory Multiprocessors. Synchronization. Models of Memory Consistency. Snooping based Cache Coherence. Directory based Cache Coherence. Data Level Parallelism. Vector Architectures. SIMD instruction set extensions. Graphics Processing Units. Storage. Input/Output.