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טכנולוגיות מיקרו וננו אלקטרוניקה
Microelectronics |
0512-4700-03 | ||||||||||||||||||||||||
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הנדסה | תואר ראשון - חשמל ואלקטרוניקה | |||||||||||||||||||||||||
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Syllabus – Micro/Nano technologies
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Lecture
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Date/Time (min)
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Title
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Content
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1.
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60
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Introduction
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Historical review and milestones, fabrication concepts, scaling, ITRS concepts
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2
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120
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Lithography I
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Principles of optical lithography –
Exposure: light sources, High pressure Hg arc lamps and Excimer lasers, masks, image modeling, aberrations,
Photoresist principles and modeling. The basic ABC model and its modification. FEM – dose and focus.
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3
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180
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Lithography II
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Tools: Steppers and step and scans,
Next generation lithography (NGL) – 157 nm immersion litho, EUV,EBL, IBL, XRL, Soft Litho and SPL.
Advanced Litho: Sub 45 nm processes, Double patterning,
Metrology and process control.
Other methods and nanolithography.
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4
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180
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Doping & Junction formation I
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Ion implantation: Principles, interaction of energetic ions and matter, modeling and tools. Monte Carlo simulation of II.
Modeling of II in Si – shallow and deep implants
Ion implanters – tools outline and methods..
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5
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120
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Doping & Junction formation II
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Principles – diffusion equations, high concentration diffusion, effect of charged vacancies and interstitials, surface effects, 2D and 3D effects in highly dense circuits, examples for Source/Drain junction formation, well formation,
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6
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60
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Rapid Thermal Processing
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Fast thermal processes, rapid heating methods, irradiative heating, rapid temperature measurement
Rapid thermal oxidation and nitridation.
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720
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Cont.
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Lecture
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Time (min.)
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Title
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Content
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7
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120
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Oxidation
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Thermal oxidation and gate formation.
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8
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120
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Gas phase deposition – Epitaxial growth,
CVD & ALD
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Principles and modeling – amorphous and polycrystalline materials. , CVD and Epitaxial growth.
Poly silicon – nucleation and growth, grain structure effect of silicidation.
Silicon dioxide - high and low temperatures, precursor effects, Nitrided oxide,
Silicon nitride, Tungsten and high-K gate materials
PECVD of oxide and low-K interlevel dielectrics
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9
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120
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Metallization I
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Contact formation
Silicides and the Silicdation process – contacts to ultra shallow contacts – examples of Co, Ti and Ni silicides
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10
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120
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Metallization II
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Interconnect processes: metal and dielectric deposition
Methods
1. Physical Vapor deposition (PVD) - Principles of evaporation and sputtering, various methods, modeling of sputtering, step coverage, deposition on sub 45 structures.
2. Electro-chemical-deposition (ECD)
3. Electroless plating
Functions
Conductors – Al, Cu
Barrier layers – Ta/Tan, CoWP
Capping layers – conducting, dielectrics
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11
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120
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Etching & cleaning I
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Wet etch– modeling and principles,
Wet clean
Dry etch – plasma etch, RIE, DRIE.
Etching process modules of silicon, oxide, metals and inter level dielectric
Trimming and APC
End point detection.
Microloading. Challenging etch - HKMG
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600
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Cont.
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Lecture
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Time
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Title
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Content
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12
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90
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CMP
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Slurry types
End points and integrated metrology
CMP needs and challenges (Oxide, Cu, Poly, etc)
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13
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90
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Process integration
front end
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MOS transistor process: HKMG (different schemes), FINFET, stressors
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14
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90
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Process integration
Backend
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Some reliability issues- voids, electromigration
Planarization issues – Chemical mechanical polishing.
Interconnects, Damascene process – seed layers, barrier laser, capping layers.
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15
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90
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Metrology and defect evaluation
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Metrology methods for insulators and metals
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16
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60
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3D Integration
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Basic 3D integration principles – the next promising technology for CMOS
Through Silicon Via
Process variations
Tools and prospects
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17
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60
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Advanced CMOS process – sub 22 nm technologies
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ITRS again – critical issues and future bottlenecks.
Theoretical imitations – material issues, quantum and thermo dynamical issues,
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Total
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480
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