סילבוס הקורס טכנולוגיות מיקרו וננו אלקטרוניקה - תש"ף, פקולטה להנדסה, אוניברסיטת ת"א

שנה"ל תש"ף

טכנולוגיות מיקרו וננו אלקטרוניקה
Microelectronics

0512-4700

הנדסה | תואר ראשון - חשמל ואלקטרוניקה

הצג קבוצות

קבוצה 01

סמ' א'

1500-1800

'א

001

עבודה סוציאלית

שיעור

פרופ שחם יוסף יעקב

הצג סילבוס

הקורס מועבר באנגלית

D:\Inetpub\shared\yedion\syllabus\05\2019\0512\0512470001_desc.txt

סילבוס מקוצר

שעות: 4 ש"ס

משקל: 3.5

דרישות קדם: התקנים אלקטרוניים

תהליכי ייצור-כללי, המבנה הגבישי של סיליקון, פגמי סיליקון, תהליכי ייצור סיליקון

(FZ,CZ), השתלת יונים, דיפוזיה, נידוף וגידול שכבות דקות (נידוף, ספטריניג, CVD, PECVD, חמצון סיליקון), תהליכי עיבוד (איכול רטוב, איכול יבש-פיזיקלי, כימי ו-RIE), פוטוליטוגרפיה, ציפויים מוליכים, מגעים חשמליים, טכנולוגיית התקנים (ביפולרית BIMOS, pMOS, nMOS ), נצילות ואמינות התקנים מיקרואלקטרוניים, שיטות CAD וכללי תכנון.

Course description

Credit points: 3.5
Prerequisites: Electronic Devices
This course covers all major microfabrication processes: General overview of the microfabrication technology. The structures of crystals and the silicon crystal, defects in crystals, fabrication processes of silicon crystals (CZ, FZ). Ion implantation. Diffusion. Thin layers: Evaporation, sputtering, CVD, PECVD, oxidation. Etching processes: Wet etching, dry etching (physical, chemical, RIE, DRIE). Photolithography. Conducting coatings. Electrical contacts and packaging: Wire bonding, flip-chip, wafer scale packaging. Overview of the Bipolar and CMOS technology in light of the subjects studied. Overview of MEMS in light of the subjects studies. Yield and reliability of the VLSI technology. Basic CAD for VLSI.

Goals

1. Micro and Nano fabrication process principles

2. Basic physics, chemistry

3. Process integration

4. Tools and methods

5. Metrology challenges

6. Trends and prospects

Each lecture, even it is specifically mentioned below, will start with basic principles, modeling, and continues with manufacturing, tools and methods and finally with metrology need and challenges, metrology tools and methods.

Syllabus – Micro/Nano technologies
Lecture	Date/Time (min)	Title	Content
1.	60	Introduction	Historical review and milestones, fabrication concepts, scaling, ITRS concepts
2	120	Lithography I	Principles of optical lithography – Exposure: light sources, High pressure Hg arc lamps and Excimer lasers, masks, image modeling, aberrations, Photoresist principles and modeling. The basic ABC model and its modification. FEM – dose and focus.
3	180	Lithography II	Tools: Steppers and step and scans, Next generation lithography (NGL) – 157 nm immersion litho, EUV,EBL, IBL, XRL, Soft Litho and SPL. Advanced Litho: Sub 45 nm processes, Double patterning, Metrology and process control. Other methods and nanolithography.
4	180	Doping & Junction formation I	Ion implantation: Principles, interaction of energetic ions and matter, modeling and tools. Monte Carlo simulation of II. Modeling of II in Si – shallow and deep implants Ion implanters – tools outline and methods..
5	120	Doping & Junction formation II	Principles – diffusion equations, high concentration diffusion, effect of charged vacancies and interstitials, surface effects, 2D and 3D effects in highly dense circuits, examples for Source/Drain junction formation, well formation,
6	60	Rapid Thermal Processing	Fast thermal processes, rapid heating methods, irradiative heating, rapid temperature measurement Rapid thermal oxidation and nitridation.
	720

Cont.
Lecture	Time (min.)	Title	Content
7	120	Oxidation	Thermal oxidation and gate formation.
8	120	Gas phase deposition – Epitaxial growth, CVD & ALD	Principles and modeling – amorphous and polycrystalline materials. , CVD and Epitaxial growth. Poly silicon – nucleation and growth, grain structure effect of silicidation. Silicon dioxide - high and low temperatures, precursor effects, Nitrided oxide, Silicon nitride, Tungsten and high-K gate materials PECVD of oxide and low-K interlevel dielectrics
9	120	Metallization I	Contact formation Silicides and the Silicdation process – contacts to ultra shallow contacts – examples of Co, Ti and Ni silicides
10	120	Metallization II	Interconnect processes: metal and dielectric deposition Methods 1. Physical Vapor deposition (PVD) - Principles of evaporation and sputtering, various methods, modeling of sputtering, step coverage, deposition on sub 45 structures. 2. Electro-chemical-deposition (ECD) 3. Electroless plating Functions Conductors – Al, Cu Barrier layers – Ta/Tan, CoWP Capping layers – conducting, dielectrics
11	120	Etching & cleaning I	Wet etch– modeling and principles, Wet clean Dry etch – plasma etch, RIE, DRIE. Etching process modules of silicon, oxide, metals and inter level dielectric Trimming and APC End point detection. Microloading. Challenging etch - HKMG
	600

Cont.
Lecture	Time	Title	Content
12	90	CMP	Slurry types End points and integrated metrology CMP needs and challenges (Oxide, Cu, Poly, etc)
13	90	Process integration front end	MOS transistor process: HKMG (different schemes), FINFET, stressors
14	90	Process integration Backend	Some reliability issues- voids, electromigration Planarization issues – Chemical mechanical polishing. Interconnects, Damascene process – seed layers, barrier laser, capping layers.
15	90	Metrology and defect evaluation	Metrology methods for insulators and metals
16	60	3D Integration	Basic 3D integration principles – the next promising technology for CMOS Through Silicon Via Process variations Tools and prospects
17	60	Advanced CMOS process – sub 22 nm technologies	ITRS again – critical issues and future bottlenecks. Theoretical imitations – material issues, quantum and thermo dynamical issues,
Total	480

קבוצה 02

סמ' א'

1800-1900

'א

104

הנדסת תוכנה

תרגיל

גב' דותן טלי

הצג סילבוס

הקורס מועבר באנגלית

D:\Inetpub\shared\yedion\syllabus\05\2019\0512\0512470002_desc.txt

סילבוס מקוצר

שעות: 4 ש"ס

משקל: 3.5

דרישות קדם: התקנים אלקטרוניים

תהליכי ייצור-כללי, המבנה הגבישי של סיליקון, פגמי סיליקון, תהליכי ייצור סיליקון

Course description

Goals

1. Micro and Nano fabrication process principles

2. Basic physics, chemistry

3. Process integration

4. Tools and methods

5. Metrology challenges

6. Trends and prospects

Syllabus – Micro/Nano technologies
Lecture	Date/Time (min)	Title	Content
1.	60	Introduction	Historical review and milestones, fabrication concepts, scaling, ITRS concepts
2	120	Lithography I	Principles of optical lithography – Exposure: light sources, High pressure Hg arc lamps and Excimer lasers, masks, image modeling, aberrations, Photoresist principles and modeling. The basic ABC model and its modification. FEM – dose and focus.
3	180	Lithography II	Tools: Steppers and step and scans, Next generation lithography (NGL) – 157 nm immersion litho, EUV,EBL, IBL, XRL, Soft Litho and SPL. Advanced Litho: Sub 45 nm processes, Double patterning, Metrology and process control. Other methods and nanolithography.
4	180	Doping & Junction formation I	Ion implantation: Principles, interaction of energetic ions and matter, modeling and tools. Monte Carlo simulation of II. Modeling of II in Si – shallow and deep implants Ion implanters – tools outline and methods..
5	120	Doping & Junction formation II	Principles – diffusion equations, high concentration diffusion, effect of charged vacancies and interstitials, surface effects, 2D and 3D effects in highly dense circuits, examples for Source/Drain junction formation, well formation,
6	60	Rapid Thermal Processing	Fast thermal processes, rapid heating methods, irradiative heating, rapid temperature measurement Rapid thermal oxidation and nitridation.
	720

Cont.
Lecture	Time (min.)	Title	Content
7	120	Oxidation	Thermal oxidation and gate formation.
8	120	Gas phase deposition – Epitaxial growth, CVD & ALD	Principles and modeling – amorphous and polycrystalline materials. , CVD and Epitaxial growth. Poly silicon – nucleation and growth, grain structure effect of silicidation. Silicon dioxide - high and low temperatures, precursor effects, Nitrided oxide, Silicon nitride, Tungsten and high-K gate materials PECVD of oxide and low-K interlevel dielectrics
9	120	Metallization I	Contact formation Silicides and the Silicdation process – contacts to ultra shallow contacts – examples of Co, Ti and Ni silicides
10	120	Metallization II	Interconnect processes: metal and dielectric deposition Methods 1. Physical Vapor deposition (PVD) - Principles of evaporation and sputtering, various methods, modeling of sputtering, step coverage, deposition on sub 45 structures. 2. Electro-chemical-deposition (ECD) 3. Electroless plating Functions Conductors – Al, Cu Barrier layers – Ta/Tan, CoWP Capping layers – conducting, dielectrics
11	120	Etching & cleaning I	Wet etch– modeling and principles, Wet clean Dry etch – plasma etch, RIE, DRIE. Etching process modules of silicon, oxide, metals and inter level dielectric Trimming and APC End point detection. Microloading. Challenging etch - HKMG
	600

Cont.
Lecture	Time	Title	Content
12	90	CMP	Slurry types End points and integrated metrology CMP needs and challenges (Oxide, Cu, Poly, etc)
13	90	Process integration front end	MOS transistor process: HKMG (different schemes), FINFET, stressors
14	90	Process integration Backend	Some reliability issues- voids, electromigration Planarization issues – Chemical mechanical polishing. Interconnects, Damascene process – seed layers, barrier laser, capping layers.
15	90	Metrology and defect evaluation	Metrology methods for insulators and metals
16	60	3D Integration	Basic 3D integration principles – the next promising technology for CMOS Through Silicon Via Process variations Tools and prospects
17	60	Advanced CMOS process – sub 22 nm technologies	ITRS again – critical issues and future bottlenecks. Theoretical imitations – material issues, quantum and thermo dynamical issues,
Total	480

קבוצה 03

סמ' א'

1100-1200

'ה

103

הנדסת תוכנה

תרגיל

גב' דותן טלי

הצג סילבוס

הקורס מועבר באנגלית

D:\Inetpub\shared\yedion\syllabus\05\2019\0512\0512470003_desc.txt

סילבוס מקוצר

שעות: 4 ש"ס

משקל: 3.5

דרישות קדם: התקנים אלקטרוניים

תהליכי ייצור-כללי, המבנה הגבישי של סיליקון, פגמי סיליקון, תהליכי ייצור סיליקון

Course description

Goals

1. Micro and Nano fabrication process principles

2. Basic physics, chemistry

3. Process integration

4. Tools and methods

5. Metrology challenges

6. Trends and prospects

Syllabus – Micro/Nano technologies
Lecture	Date/Time (min)	Title	Content
1.	60	Introduction	Historical review and milestones, fabrication concepts, scaling, ITRS concepts
2	120	Lithography I	Principles of optical lithography – Exposure: light sources, High pressure Hg arc lamps and Excimer lasers, masks, image modeling, aberrations, Photoresist principles and modeling. The basic ABC model and its modification. FEM – dose and focus.
3	180	Lithography II	Tools: Steppers and step and scans, Next generation lithography (NGL) – 157 nm immersion litho, EUV,EBL, IBL, XRL, Soft Litho and SPL. Advanced Litho: Sub 45 nm processes, Double patterning, Metrology and process control. Other methods and nanolithography.
4	180	Doping & Junction formation I	Ion implantation: Principles, interaction of energetic ions and matter, modeling and tools. Monte Carlo simulation of II. Modeling of II in Si – shallow and deep implants Ion implanters – tools outline and methods..
5	120	Doping & Junction formation II	Principles – diffusion equations, high concentration diffusion, effect of charged vacancies and interstitials, surface effects, 2D and 3D effects in highly dense circuits, examples for Source/Drain junction formation, well formation,
6	60	Rapid Thermal Processing	Fast thermal processes, rapid heating methods, irradiative heating, rapid temperature measurement Rapid thermal oxidation and nitridation.
	720

Cont.
Lecture	Time (min.)	Title	Content
7	120	Oxidation	Thermal oxidation and gate formation.
8	120	Gas phase deposition – Epitaxial growth, CVD & ALD	Principles and modeling – amorphous and polycrystalline materials. , CVD and Epitaxial growth. Poly silicon – nucleation and growth, grain structure effect of silicidation. Silicon dioxide - high and low temperatures, precursor effects, Nitrided oxide, Silicon nitride, Tungsten and high-K gate materials PECVD of oxide and low-K interlevel dielectrics
9	120	Metallization I	Contact formation Silicides and the Silicdation process – contacts to ultra shallow contacts – examples of Co, Ti and Ni silicides
10	120	Metallization II	Interconnect processes: metal and dielectric deposition Methods 1. Physical Vapor deposition (PVD) - Principles of evaporation and sputtering, various methods, modeling of sputtering, step coverage, deposition on sub 45 structures. 2. Electro-chemical-deposition (ECD) 3. Electroless plating Functions Conductors – Al, Cu Barrier layers – Ta/Tan, CoWP Capping layers – conducting, dielectrics
11	120	Etching & cleaning I	Wet etch– modeling and principles, Wet clean Dry etch – plasma etch, RIE, DRIE. Etching process modules of silicon, oxide, metals and inter level dielectric Trimming and APC End point detection. Microloading. Challenging etch - HKMG
	600

Cont.
Lecture	Time	Title	Content
12	90	CMP	Slurry types End points and integrated metrology CMP needs and challenges (Oxide, Cu, Poly, etc)
13	90	Process integration front end	MOS transistor process: HKMG (different schemes), FINFET, stressors
14	90	Process integration Backend	Some reliability issues- voids, electromigration Planarization issues – Chemical mechanical polishing. Interconnects, Damascene process – seed layers, barrier laser, capping layers.
15	90	Metrology and defect evaluation	Metrology methods for insulators and metals
16	60	3D Integration	Basic 3D integration principles – the next promising technology for CMOS Through Silicon Via Process variations Tools and prospects
17	60	Advanced CMOS process – sub 22 nm technologies	ITRS again – critical issues and future bottlenecks. Theoretical imitations – material issues, quantum and thermo dynamical issues,
Total	480

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