Prerequisites: Computer Organization

 

In this lab we'll design and implement an embedded system, suited for integration into ASIC SoC. We'll learn hierarchical design methodology with emphasis on verification, enhancing the processor core using high level ISA simulator, low level cycle accurate simulator, and the verilog hardware description language. We'll start with a simple RISC processor, and enhance it with superscalar units, pipe-lining, branch prediction, hardware accelerators, SIMD instructions, virtual memory and cache.

 

 

design methodology with emphasis on verification, implementing the processor in high level ISA simulator, low level cycle

accurate simulator, and the verilog hardware description language. We'll start with a simple RISC processor, and enhance it

with superscalar units, pipe-lining, branch prediction, hardware accelerators, SIMD instructions, virtual memory and cache.

Lab #1: Introduction to verilog

Lab #2,#3: High level ISA RISC simple processor simulator

Lab #4: Low level cycle accurate simple processor simulator

Lab #5: Verilog simple processor implementation

Lab #6: Review and complete previous lab assignments

Lab #7: Verilog simple processor verification

Lab #8,#9: Pipelining the processor, branch prediction

Lab #10: Hardware accelerators, SIMD

Lab #11: Review and complete previous lab assignments

Lab #12,#13: Memory hierarchy, virtual memory and cache

Lab #14: Project

 

 Prerequisites: Computer Organization

 

In this lab we'll design and implement an embedded system, suited for integration into ASIC SoC. We'll learn hierarchical design methodology with emphasis on verification, enhancing the processor core using high level ISA simulator, low level cycle accurate simulator, and the verilog hardware description language. We'll start with a simple RISC processor, and enhance it with superscalar units, pipe-lining, branch prediction, hardware accelerators, SIMD instructions, virtual memory and cache.

 

 

design methodology with emphasis on verification, implementing the processor in high level ISA simulator, low level cycle

accurate simulator, and the verilog hardware description language. We'll start with a simple RISC processor, and enhance it

with superscalar units, pipe-lining, branch prediction, hardware accelerators, SIMD instructions, virtual memory and cache.

Lab #1: Introduction to verilog

Lab #2,#3: High level ISA RISC simple processor simulator

Lab #4: Low level cycle accurate simple processor simulator

Lab #5: Verilog simple processor implementation

Lab #6: Review and complete previous lab assignments

Lab #7: Verilog simple processor verification

Lab #8,#9: Pipelining the processor, branch prediction

Lab #10: Hardware accelerators, SIMD

Lab #11: Review and complete previous lab assignments

Lab #12,#13: Memory hierarchy, virtual memory and cache

Lab #14: Project