Writing fast and scalable multi-core programs is hard. Multi-core programming models fail to abstract away the details of the underlying computer architecture, partly because of limitations in the hardware/software interfaces (such as instruction sets and memory models). We must thus understand the multi-core architecture, both to design efficient algorithms and systems, and to find better abstractions and interfaces.

This course covers the state of the art in multi-core programming and architecture. A main objective is to introduce students to open research problems in multi-core research.

NOTE: We will consider hardware only at the microarchitecture level, not at the logic/gate level; for an example of microarchitectural material, see the book A Primer on Memory Consistency and Cache Coherence.

List of Topics

- Reasoning about concurrent algorithms

- Cache coherence protocols

- Efficient serialization (locking and advanced techniques)

- Memory consistency models (of processors and programming languages)

• Processors: x86 (Intel/AMD), ARM and IBM POWER
• Language: Java and C/C++
• Efficient implementations of strong memory models

- Speculative execution attacks and defences

- Safe memory reclamation

- Transactional memory

- Concurrent search trees

- Ordered parallelism (priority-based scheduling)

• Algorithms and architectural support

- Relaxing correctness guarantees of concurrent data structures to improve their performance

Requirements

• Research project (no exam)
• Home assignments